Cross-correlation

The cross-multiplication in the correlator boards is a challenging task, as there are more than 500,000 signal pairs to be combined; efficient signal routing is at a premium. The design keeps signal replication at the lowest possible logical level, primarily within a local region inside of each (Xilinx Virtex-4 SX-35) FPGA. The FPGA is broken down into 136 correlation "cells", each of which in turn processes a 16x16 array of input signals. The cell processing is time-multiplexed, in order to match the 256 MHz processing speed of the dedicated multipliers in the FPGA to the slower channel data rate of 10^4 complex frequency samples per second.

Overall the output from the correlator consists of about 3 billion complex visibility points dumped per second over a total of 256 gigE cables (V. 1 of the firmware will integrate 4 adjacent 10 KHz channels into one 40 KHz, thus cutting the output flow by a factor of 4). The visibility data are formed into images by the realtime software system residing on the realtime computer.